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    SLIP
    2009
    ACM
    226views Computer Networks» more  SLIP 2009»
    Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
    13 years 11 months ago
    Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
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    Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
    Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
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