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MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
13 years 9 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
13 years 9 months ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...
MTDT
2003
IEEE
83views Hardware» more  MTDT 2003»
13 years 9 months ago
A Fault Primitive Based Analysis of Linked Faults in RAMs
: Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characteri...
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
MTDT
2003
IEEE
124views Hardware» more  MTDT 2003»
13 years 9 months ago
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
Zaid Al-Ars, A. J. van de Goor
MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
13 years 9 months ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken