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ISCAS
2007
IEEE
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9 years 10 months ago
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when b...
Xiang Gao, Eric A. M. Klumperink, Bram Nauta
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