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VTS
2007
IEEE
203views Hardware» more  VTS 2007»
13 years 10 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba
DAC
2008
ACM
14 years 4 months ago
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
1 Soft errors induced by radiation are an increasing problem in the microelectronic field. Although traditional models estimate the reliability of memories suffering Single Event U...
Juan Antonio Maestro, Pedro Reviriego