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TVLSI
2002
107views more  TVLSI 2002»
9 years 28 days ago
Low-power clock distribution using multiple voltages and reduced swings
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...
Jatuchai Pangjun, Sachin S. Sapatnekar
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
9 years 6 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
GLVLSI
2005
IEEE
144views VLSI» more  GLVLSI 2005»
9 years 7 months ago
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
ICPPW
2007
IEEE
9 years 7 months ago
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
Gang Qu
ICCD
2002
IEEE
137views Hardware» more  ICCD 2002»
9 years 10 months ago
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...
Stephanie Augsburger, Borivoje Nikolic
ICCD
2003
IEEE
105views Hardware» more  ICCD 2003»
9 years 10 months ago
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
DAC
2003
ACM
10 years 2 months ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...
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