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ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
10 years 7 days ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
DATE
2010
IEEE
118views Hardware» more  DATE 2010»
10 years 15 days ago
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Due to fast technology scaling, negative bias temperature instability (NBTI) has become a major reliability concern in designing modern integrated circuits. In this paper, we prese...
Lin Li, Youtao Zhang, Jun Yang 0002, Jianhua Zhao
DAC
2004
ACM
10 years 2 months ago
A dual-core 64b ultraSPARC microprocessor for dense server applications
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an effic...
Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petri...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
10 years 3 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DAC
2006
ACM
10 years 4 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
Rakesh Vattikonda, Wenping Wang, Yu Cao
ISQED
2006
IEEE
259views Hardware» more  ISQED 2006»
10 years 4 months ago
Impact of NBTI on SRAM Read Stability and Design for Reliability
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
10 years 5 months ago
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase ...
Bin Zhang, Michael Orshansky
GLVLSI
2008
IEEE
128views VLSI» more  GLVLSI 2008»
10 years 5 months ago
NBTI-aware flip-flop characterization and design
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
Hamed Abrishami, Safar Hatami, Behnam Amelifard, M...
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
10 years 5 months ago
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
10 years 5 months ago
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
— Negative Bias Temperature Instability (NBTI) is a leading reliability concern for integrated circuits (ICs). It gradually increases the threshold voltages of PMOS transistors, ...
Lide Zhang, Robert P. Dick
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