Sciweavers

NOCS
2007
IEEE
13 years 9 months ago
Approaching Ideal NoC Latency with Pre-Configured Routes
George Michelogiannakis, Dionisios N. Pnevmatikato...
NOCS
2007
IEEE
13 years 10 months ago
Towards Open Network-on-Chip Benchmarks
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challe...
Cristian Grecu, André Ivanov, Partha Pratim...
NOCS
2007
IEEE
13 years 10 months ago
Implementing DSP Algorithms with On-Chip Networks
Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs n...
Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud
NOCS
2007
IEEE
13 years 10 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
NOCS
2007
IEEE
13 years 10 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
NOCS
2007
IEEE
13 years 10 months ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
NOCS
2007
IEEE
13 years 10 months ago
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...
Zied Marrakchi, Hayder Mrabet, Christian Masson, H...
NOCS
2007
IEEE
13 years 10 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
NOCS
2007
IEEE
13 years 10 months ago
Transaction-Based Communication-Centric Debug
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
Kees Goossens, Bart Vermeulen, Remco van Steeden, ...