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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 10 months ago
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition
This paper addresses two problems related to disjointsupport decomposition of Boolean functions. First, we present a heuristic for finding a subset of variables, X, which results...
Andrés Martinelli, Elena Dubrova
DSD
2008
IEEE
115views Hardware» more  DSD 2008»
13 years 11 months ago
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
Petr Fiser, Pavel Kubalík, Hana Kubatova