Sciweavers

Share
GECCO
2003
Springer
124views Optimization» more  GECCO 2003»
10 years 5 months ago
ERA: An Algorithm for Reducing the Epistasis of SAT Problems
A novel method, for solving satis´Čüability (SAT) instances is presented. It is based on two components: a) An Epistasis Reducer Algorithm (ERA) that produces a more suited represe...
Eduardo Rodriguez-Tello, Jose Torres-Jimenez
DAC
2006
ACM
11 years 22 days ago
Efficient SAT-based Boolean matching for FPGA technology mapping
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler...
books