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    ARVLSI
    1997
    IEEE
    104views VLSI» more  ARVLSI 1997»
    A High-Speed Asynchronous Decompression Circuit for Embedded Processors
    13 years 8 months ago
    A High-Speed Asynchronous Decompression Circuit for Embedded Processors
    Download  www.cs.columbia.edu
    This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
    Martin Benes, Andrew Wolfe, Steven M. Nowick
    claim paper
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