VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
ICCD
2003
IEEE
13 years 9 months ago
2003
IEEE
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
VTS
2008
IEEE
13 years 11 months ago
2008
IEEE
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...