Sciweavers

TCAD
2008
73views more  TCAD 2008»
13 years 4 months ago
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias
Abstract--In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures...
Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
ASPDAC
2008
ACM
174views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
13 years 8 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
DAC
1996
ACM
13 years 8 months ago
Computing Parametric Yield Adaptively Using Local Linear Models
Abstract A divide-and-conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could...
Mien Li, Linda S. Milor
GLVLSI
2005
IEEE
205views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Optimization objectives and models of variation for statistical gate sizing
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...
CODES
2006
IEEE
13 years 10 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...