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VTS
2000
IEEE
94views Hardware» more  VTS 2000»
8 years 10 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
8 years 11 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao
ATS
2003
IEEE
151views Hardware» more  ATS 2003»
8 years 11 months ago
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
Junhao Shi, Görschwin Fey, Rolf Drechsler
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
9 years 16 days ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the signi´Čücance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
9 years 3 months ago
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...
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