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ET
2010
98views more  ET 2010»
8 years 9 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
DAC
2005
ACM
9 years 10 days ago
Path delay test compaction with process variation tolerance
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, T...
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
9 years 2 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
9 years 2 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel
DATE
1999
IEEE
91views Hardware» more  DATE 1999»
9 years 2 months ago
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the Integrate...
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniota...
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
9 years 3 months ago
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
9 years 3 months ago
Exact Grading of Multiple Path Delay Faults
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
Saravanan Padmanaban, Spyros Tragoudas
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
9 years 3 months ago
Non-Enumerative Path Delay Fault Diagnosis
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
Saravanan Padmanaban, Spyros Tragoudas
ATS
2005
IEEE
98views Hardware» more  ATS 2005»
9 years 4 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
9 years 4 months ago
A dynamic test compaction procedure for high-quality path delay testing
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, T...
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