Sciweavers

Share
HPCA
2012
IEEE
8 years 3 months ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
8 years 11 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
IJPP
2008
72views more  IJPP 2008»
9 years 8 months ago
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challen...
Gabriel H. Loh, Daniel A. Jiménez
CASES
2008
ACM
9 years 10 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
9 years 11 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
9 years 11 months ago
Very low power pipelines using significance compression
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
Ramon Canal, Antonio González, James E. Smi...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
10 years 2 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
ISCAS
2007
IEEE
107views Hardware» more  ISCAS 2007»
10 years 2 months ago
Architecture Level Power-Performance Tradeoffs for Pipelined Designs
Abstract—This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It w...
Haider Ali, Bashir M. Al-Hashimi
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
10 years 2 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
DAC
2003
ACM
10 years 9 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
books