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    DDECS
    2007
    IEEE
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    Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
    13 years 11 months ago
    Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
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    — This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
    Lukás Sekanina
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