ASPDAC
1995
ACM
13 years 8 months ago
1995
ACM
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
PATMOS
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
PACS
2000
Springer
13 years 8 months ago
2000
Springer
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
EVOW
2000
Springer
13 years 8 months ago
2000
Springer
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
CEC
2003
IEEE
13 years 8 months ago
2003
IEEE
Most embedded systemshave tightconstraints on power consumption because the amonnt of power available to these systems is limited due to the limitation ofbattery life. For this rea...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
DSD
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...