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SAC
2008
ACM
9 years 6 months ago
Power-efficient and scalable load/store queue design via address compression
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen
CORR
2008
Springer
112views Education» more  CORR 2008»
9 years 6 months ago
Ni-MH battery modelling for ambient intelligence applications
Mobile devices, like sensor networks and MEMS actuators use mobile power supplies to ensure energy for their operation. These are mostly batteries. The lifetime of the devices dep...
Domonkos Szente-Varga, Gyula Horvath, Márta...
TCAD
2002
104views more  TCAD 2002»
9 years 6 months ago
An instruction-level energy model for embedded VLIW architectures
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
TVLSI
1998
81views more  TVLSI 1998»
9 years 6 months ago
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to ef...
Chuan-Yu Wang, Kaushik Roy
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
9 years 6 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
9 years 6 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
JSA
2000
96views more  JSA 2000»
9 years 6 months ago
Design techniques for low-power systems
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power d...
Paul J. M. Havinga, Gerard J. M. Smit
CC
2002
Springer
131views System Software» more  CC 2002»
9 years 6 months ago
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
Andrea G. M. Cilio, Henk Corporaal
COMCOM
2004
142views more  COMCOM 2004»
9 years 6 months ago
An adaptive power-conserving service discipline for bluetooth (APCB) wireless networks
Bluetooth is a new short-range radio technology to form a small wireless system. In most of the current Bluetooth products, the master polls the slaves in a round robin manner and...
Hao Zhu, Guohong Cao, George Kesidis, Chita R. Das
TVLSI
2008
139views more  TVLSI 2008»
9 years 6 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
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