Sciweavers

IPPS
2010
IEEE
13 years 27 days ago
A simple thermal model for multi-core processors and its application to slack allocation
Abstract--Power density and heat density of multicore processor system are increasing exponentially with Moore's Law. High temperature on chip greatly affects its reliability,...
Zhe Wang, Sanjay Ranka
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 3 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
IJES
2007
92views more  IJES 2007»
13 years 3 months ago
Exploring temperature-aware design in low-power MPSoCs
: The power density in high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating ‘hot spotsâ€...
Giacomo Paci, Francesco Poletti, Luca Benini, Paul...
CORR
2008
Springer
61views Education» more  CORR 2008»
13 years 3 months ago
Design Methodology and Manufacture of a Microinductor
Potential core materials to supersede ferrite in the 0.5-10 MHz frequency range are investigated. The performance of electrodeposited nickel-iron, cobalt-iron-copper alloys and the...
David Flynn, Marc P. Y. Desmulliez
DATE
2004
IEEE
132views Hardware» more  DATE 2004»
13 years 7 months ago
Hybrid Architectural Dynamic Thermal Management
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
Kevin Skadron
ASPLOS
2004
ACM
13 years 9 months ago
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
Mohamed A. Gomaa, Michael D. Powell, T. N. Vijayku...
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
13 years 9 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
14 years 17 days ago
Thermal-Aware Clustered Microarchitectures
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
Pedro Chaparro, José González, Anton...
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 4 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...