Sciweavers

TSP
2008
123views more  TSP 2008»
13 years 3 months ago
A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
Shu Xiao, Edmund Ming-Kit Lai
PACS
2000
Springer
83views Hardware» more  PACS 2000»
13 years 7 months ago
A Comparison of Two Architectural Power Models
Reducing power, on both a per cycle basis and as the total energy used over the lifetime of an application, has become more important as small and embedded devices become increasi...
Soraya Ghiasi, Dirk Grunwald
DSD
2006
IEEE
107views Hardware» more  DSD 2006»
13 years 9 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
13 years 9 months ago
An analytical state dependent leakage power model for FPGAs
In this paper we present a state dependent analytical leakage power model for FPGAs. The model accounts for subthreshold leakage and gate leakage in FPGAs, since these are the two...
Akhilesh Kumar, Mohab Anis
IPPS
2008
IEEE
13 years 10 months ago
Modeling and analysis of power in multicore network processors
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing signi...
S. Huang, Y. Luo, W. Feng
SLIP
2009
ACM
13 years 10 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic