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TCAD
2010
97views more  TCAD 2010»
8 years 8 months ago
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
TCAD
2008
172views more  TCAD 2008»
9 years 1 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
9 years 3 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He
PACS
2000
Springer
118views Hardware» more  PACS 2000»
9 years 5 months ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
ISLPED
1996
ACM
109views Hardware» more  ISLPED 1996»
9 years 5 months ago
Transition reduction in carry-save adder trees
-- By taking advantage of the redundancy in a 4-2 compressor, we reduce the number of transitions in carry-save adder trees that are common in large multipliers. Three new 4-2 comp...
Patrik Larsson, Chris J. Nicol
DAC
1996
ACM
9 years 5 months ago
Desensitization for Power Reduction in Sequential Circuits
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
Xiangfeng Chen, Peichen Pan, C. L. Liu
DATE
1999
IEEE
74views Hardware» more  DATE 1999»
9 years 5 months ago
FSMD Functional Partitioning for Low Power
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
Enoch Hwang, Frank Vahid, Yu-Chin Hsu
DAC
1999
ACM
9 years 5 months ago
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems
Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper ...
Youngsoo Shin, Kiyoung Choi
ISLPED
2000
ACM
94views Hardware» more  ISLPED 2000»
9 years 5 months ago
Operating-system directed power reduction
This paper presents a new approach for power reduction by taking a global, software-centric view. It analyzes the sources of power consumption: tasks that require services from ha...
Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
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