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HPCA
2011
IEEE
11 years 3 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISM
2006
IEEE
130views Multimedia» more  ISM 2006»
11 years 11 months ago
Scheduling Data Delivery in Heterogeneous Wireless Sensor Networks
In this paper we present a proxy-level scheduler that can significantly improve QoS in heterogeneous wireless sensor networks while at the same time reducing the overall power con...
Daeseob Lim, Jaewook Shim, Tajana Simunic Rosing, ...
DATE
2004
IEEE
151views Hardware» more  DATE 2004»
12 years 3 months ago
Dynamic Voltage and Cache Reconfiguration for Low Power
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
André C. Nácul, Tony Givargis
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
12 years 4 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...
RTSS
2003
IEEE
12 years 5 months ago
A Dynamic Voltage Scaling Algorithm for Sporadic Tasks
Dynamic voltage scaling (DVS) algorithms save energy by scaling down the processor frequency when the processor is not fully loaded. Many algorithms have been proposed for periodi...
Ala' Qadi, Steve Goddard, Shane Farritor
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
12 years 5 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
12 years 5 months ago
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Mar...
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
12 years 5 months ago
Area optimization for leakage reduction and thermal stability in nanometer scale technologies
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
Ja Chun Ku, Yehea I. Ismail
ISQED
2007
IEEE
179views Hardware» more  ISQED 2007»
12 years 6 months ago
Cross Layer Error Exploitation for Aggressive Voltage Scaling
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used t...
Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Ku...
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
12 years 6 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos
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