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ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
13 years 5 months ago
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructe...
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoy...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
13 years 7 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
13 years 7 months ago
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Abstract-- With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-dr...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
ICCAD
2000
IEEE
132views Hardware» more  ICCAD 2000»
13 years 8 months ago
Frequency Domain Analysis of Switching Noise on Power Supply Network
In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network a...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
ASPDAC
2009
ACM
159views Hardware» more  ASPDAC 2009»
13 years 8 months ago
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapa...
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
13 years 8 months ago
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
13 years 9 months ago
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim...
IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
13 years 9 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
ISPD
2005
ACM
126views Hardware» more  ISPD 2005»
13 years 9 months ago
Effects of on-chip inductance on power distribution grid
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We pe...
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi O...
VTS
2005
IEEE
97views Hardware» more  VTS 2005»
13 years 9 months ago
Static Compaction of Delay Tests Considering Power Supply Noise
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...
Jing Wang 0006, Xiang Lu, Wangqi Qiu, Ziding Yue, ...