Sciweavers

VLSI
2007
Springer
13 years 10 months ago
Parametric structure-preserving model order reduction
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
Jorge Fernandez Villena, Wil H. A. Schilders, L. M...
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
13 years 10 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
13 years 10 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
ISQED
2007
IEEE
152views Hardware» more  ISQED 2007»
13 years 10 months ago
Variation Aware Timing Based Placement Using Fuzzy Programming
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
Venkataraman Mahalingam, N. Ranganathan
ISCAS
2007
IEEE
165views Hardware» more  ISCAS 2007»
13 years 10 months ago
A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design
—Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference (BGR) circuits. In this paper, we describe the design of a BG...
Juan Pablo Martinez Brito, Sergio Bampi, Hamilton ...
ISCAS
2007
IEEE
121views Hardware» more  ISCAS 2007»
13 years 10 months ago
Precise RSSI with High Process Variation Tolerance
— A receiving signal strength indicator (RSSI) built with transconductance amplifiers is presented. The RSSI achieves high tolerance to process variations by utilizing the unique...
Chao Yang, Andrew Mason
ISCAS
2008
IEEE
122views Hardware» more  ISCAS 2008»
13 years 11 months ago
A nano-CMOS process variation induced read failure tolerant SRAM cell
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
13 years 11 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
ICCAD
2008
IEEE
129views Hardware» more  ICCAD 2008»
13 years 11 months ago
Path-RO: a novel on-chip critical path delay measurement under process variations
— As technology scales to 45nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actua...
Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Dat...