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VLSISP
2008
123views more  VLSISP 2008»
8 years 11 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
HASE
1997
IEEE
9 years 3 months ago
A Mechanism for Communicating in Dynamically Reconfigurable Embedded Systems
Abstract: We present a time-bounded state-based communication mechanism for dynamically reconfigurable embedded systems. The mechanism is a single-processor, low-overhead version o...
Mehrdad Hassani, David B. Stewart
CODES
1998
IEEE
9 years 3 months ago
A hardware/software prototyping environment for dynamically reconfigurable embedded systems
Next generation embedded systems place new demands on an efficient methodology for their design and verification. These systems have to support interaction over a network, multipl...
Josef Fleischmann, Klaus Buchenrieder, Rainer Kres...
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
9 years 3 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
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