Sciweavers

DATE
1999
IEEE
92views Hardware» more  DATE 1999»
13 years 9 months ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long
HIPC
2005
Springer
13 years 10 months ago
Application of Reduce Order Modeling to Time Parallelization
We recently proposed a new approach to parallelization, by decomposing the time domain, instead of the conventional space domain. This improves latency tolerance, and we demonstrat...
Ashok Srinivasan, Yanan Yu, Namas Chandra