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    ICCAD
    1996
    IEEE
    131views Hardware» more  ICCAD 1996»
    Multi-level logic optimization for low power using local logic transformations
    13 years 9 months ago
    Multi-level logic optimization for low power using local logic transformations
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    In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
    Qi Wang, Sarma B. K. Vrudhula
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