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CC
2003
Springer
13 years 9 months ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
TLDI
2003
ACM
108views Formal Methods» more  TLDI 2003»
13 years 9 months ago
Inferring annotated types for inter-procedural register allocation with constructor flattening
We introduce an annotated type system for a compiler intermediate language. The type system is designed to support inter-procedural register allocation and the representation of t...
Torben Amtoft, Robert Muller
PLDI
2003
ACM
13 years 9 months ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume
IEEEPACT
2003
IEEE
13 years 9 months ago
Resolving Register Bank Conflicts for a Network Processor
This paper discusses a register bank assignment problem for a popular network processor--Intel's IXP. Due to limited data paths, the network processor has a restriction that ...
Xiaotong Zhuang, Santosh Pande
PLDI
2005
ACM
13 years 10 months ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Bitwidth-aware scheduling and binding in high-level synthesis
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, J...
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
13 years 10 months ago
RENO - A Rename-Based Instruction Optimizer
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
Vlad Petric, Tingting Sha, Amir Roth
CGO
2005
IEEE
13 years 10 months ago
A Progressive Register Allocator for Irregular Architectures
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
David Koes, Seth Copen Goldstein
PLDI
2006
ACM
13 years 10 months ago
A global progressive register allocator
This paper describes a global progressive register allocator, a register allocator that uses an expressive model of the register allocation problem to quickly find a good allocat...
David Ryan Koes, Seth Copen Goldstein
CGO
2006
IEEE
13 years 10 months ago
Tailoring Graph-coloring Register Allocation For Runtime Compilation
Just-in-time compilers are invoked during application execution and therefore need to ensure fast compilation times. Consequently, runtime compiler designers are averse to impleme...
Keith D. Cooper, Anshuman Dasgupta