ICCAD
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...