Sciweavers

ANCS
2007
ACM
13 years 8 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy
GLVLSI
2000
IEEE
75views VLSI» more  GLVLSI 2000»
13 years 9 months ago
A wave-pipelined router architecture using ternary associative memory
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
José G. Delgado-Frias, Jabulani Nyathi, Lax...
CODES
2007
IEEE
13 years 10 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha