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ANCS
2007
ACM
9 years 3 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy
GLVLSI
2000
IEEE
75views VLSI» more  GLVLSI 2000»
9 years 3 months ago
A wave-pipelined router architecture using ternary associative memory
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of signi´Čücantly reducing clock cycle time an...
José G. Delgado-Frias, Jabulani Nyathi, Lax...
CODES
2007
IEEE
9 years 5 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
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