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COMSUR
2011
213views Hardware» more  COMSUR 2011»
8 years 1 months ago
Securing BGP - A Literature Survey
Abstract—The Border Gateway Protocol (BGP) is the Internet’s inter-domain routing protocol. One of the major concerns related to BGP is its lack of effective security measures,...
Geoff Huston, Mattia Rossi, Grenville J. Armitage
DAC
1994
ACM
9 years 5 months ago
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture
- This paper studies the routing problem for a new Field-Programmable Gate Array (FPGA) and Field-Programmable Interconnect Chip (FPIC) routing architecture which improves upon the...
Yachyang Sun, C. L. Liu
ICCAD
1994
IEEE
106views Hardware» more  ICCAD 1994»
9 years 5 months ago
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...
Yu-Liang Wu, Douglas Chang
FPGA
1998
ACM
142views FPGA» more  FPGA 1998»
9 years 5 months ago
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
IPPS
1999
IEEE
9 years 5 months ago
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
9 years 6 months ago
Mixing buffers and pass transistors in FPGA routing architectures
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
Mike Sheng, Jonathan Rose
FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
9 years 6 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
9 years 7 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
9 years 7 months ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
9 years 8 months ago
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
Fu-Wei Chen, Yi-Yu Liu
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