Sciweavers

Share
SBACPAD
2007
IEEE
110views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
Steen Larsen, Parthasarathy Sarangam, Ram Huggahal...
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam
SBACPAD
2007
IEEE
91views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Impacts of Multiprocessor Configurations on Workloads in Bioinformatics
Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with...
Youfeng Wu, Mauricio Breternitz Jr., Victor Ying
SBACPAD
2007
IEEE
128views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Node Level Primitives for Parallel Exact Inference
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
Yinglong Xia, Viktor K. Prasanna
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
9 years 7 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
SBACPAD
2007
IEEE
554views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Ped...
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
9 years 7 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...
SBACPAD
2007
IEEE
85views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Exigency-based real-time scheduling policy to provide absolute QoS for web services
— Telemedicine, distance learning and e-commerce applications impose time constraints directly related to the efficacy of their operations. In order to offer reliability levels ...
Lucas S. Casagrande, Rodrigo Fernandes de Mello, R...
SBACPAD
2007
IEEE
157views Hardware» more  SBACPAD 2007»
9 years 7 months ago
Exploring Novel Parallelization Technologies for 3-D Imaging Applications
Multi-dimensional imaging techniques involve the processing of high resolution images commonly used in medical, civil and remote-sensing applications. A barrier commonly encounter...
Diego Rivera, Dana Schaa, Micha Moffie, David R. K...
books