Sciweavers

DATE
1998
IEEE
88views Hardware» more  DATE 1998»
13 years 8 months ago
Functional Scan Chain Testing
Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (T...
Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-...
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
13 years 8 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
13 years 8 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ISQED
2010
IEEE
121views Hardware» more  ISQED 2010»
13 years 8 months ago
A novel two-dimensional scan-control scheme for test-cost reduction
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
Chia-Yi Lin, Hung-Ming Chen
ICCD
2003
IEEE
143views Hardware» more  ICCD 2003»
13 years 9 months ago
Aggressive Test Power Reduction Through Test Stimuli Transformation
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
Ozgur Sinanoglu, Alex Orailoglu
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
13 years 9 months ago
A secure scan design methodology
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
David Hély, Frédéric Bancel, ...
DATE
2008
IEEE
139views Hardware» more  DATE 2008»
13 years 10 months ago
Scan Chain Organization for Embedded Diagnosis
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel...
Melanie Elm, Hans-Joachim Wunderlich
ATS
2009
IEEE
135views Hardware» more  ATS 2009»
13 years 10 months ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...
ATS
2009
IEEE
126views Hardware» more  ATS 2009»
13 years 10 months ago
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
—In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper w...
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai,...