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    FTCS
    1994
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    Concurrent Error Detection in Self-Timed VLSI
    13 years 6 months ago
    Concurrent Error Detection in Self-Timed VLSI
    Download  www.cs.ucla.edu
    This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
    David A. Rennels, Hyeongil Kim
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