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DAC
1991
ACM
11 years 5 months ago
A Unified Approach for the Synthesis of Self-Testable Finite State Machines
-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor ...
Bernhard Eschermann, Hans-Joachim Wunderlich
ISLPED
1997
ACM
106views Hardware» more  ISLPED 1997»
11 years 5 months ago
A sequential procedure for average power analysis of sequential circuits
A new statistical technique for average power estimation in sequential circuits is presented. Due to the feedback mechanism, conventional statistical procedures cannot be applied ...
Li-Pen Yuan, Sung-Mo Kang
ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
11 years 5 months ago
K2: an estimator for peak sustainable power of VLSI circuits
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
11 years 5 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
DAC
1995
ACM
11 years 5 months ago
Power Estimation in Sequential Circuits
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
11 years 5 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono
DAC
1996
ACM
11 years 5 months ago
Desensitization for Power Reduction in Sequential Circuits
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
Xiangfeng Chen, Peichen Pan, C. L. Liu
DAC
1997
ACM
11 years 5 months ago
ATPG for Heat Dissipation Minimization During Scan Testing
An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of l...
Seongmoon Wang, Sandeep K. Gupta
DATE
1997
IEEE
92views Hardware» more  DATE 1997»
11 years 5 months ago
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits
The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of al...
A. Dargelas, C. Gauthron, Yves Bertrand
DATE
1999
IEEE
118views Hardware» more  DATE 1999»
11 years 5 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
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