Sciweavers

Share
SIPS
2008
IEEE
8 years 9 months ago
Low-complexity high-speed 4-D TCM decoder
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture f...
Jinjin He, Zhongfeng Wang, Huaping Liu
SIPS
2008
IEEE
8 years 9 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
SIPS
2008
IEEE
8 years 9 months ago
Analysis of belief propagation for hardware realization
Belief propagation has become a popular technique for solving computer vision problems, such as stereo estimation and image denoising. However, it requires large memory and bandwi...
Chao-Chung Cheng, Chia-Kai Liang, Yen-Chieh Lai, H...
SIPS
2008
IEEE
8 years 9 months ago
Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis
This paper describes the sub-Nyquist rate digital-to-analog conversion technique for a direct waveform synthesis (DWS) transmitter. IEEE 802.22 TV band Cognitive Radio (CR) transm...
Stanley Yuan-Shih Chen, Nam-Seog Kim, Jan M. Rabae...
SIPS
2008
IEEE
8 years 9 months ago
Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition
In this paper, we present a bio-inspired unified model to improve the recognition accuracy of character recognition problems for CAPTCHA (Completely Automated Public Turing Test t...
Chi-Wei Lin, Yu-Han Chen, Liang-Gee Chen
SIPS
2008
IEEE
8 years 9 months ago
Scheduling of dataflow models within the Reconfigurable Video Coding framework
The upcoming Reconfigurable Video Coding (RVC) standard from MPEG (ISO/IEC SC29WG11) defines a library of coding tools to specify existing or new compressed video formats and deco...
Jani Boutellier, Veeranjaneyulu Sadhanala, Christo...
SIPS
2008
IEEE
8 years 9 months ago
High-throughput dual-mode single/double binary map processor design for wireless wan
In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional tur...
Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu
SIPS
2008
IEEE
8 years 9 months ago
Efficient data flow variable length decoding implementation for the MPEG reconfigurable video coding framework
In 2004, ISO/IEC SC29 better known as MPEG started a new standard initiative aiming at facilitating the deployment of multi-format video codec design and to enable the possibility...
Jianjun Li, Dandan Ding, Christophe Lucarz, Samuel...
SIPS
2008
IEEE
8 years 9 months ago
Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks
Intellectual Properties (IPs) mapping algorithms for On-Chip-Networks (OCNs) allocate a set of IPs onto given network topologies. The existing mapping algorithms limit a single IP...
Ting-Jung Lin, Shu-Yen Lin, An-Yeu Wu
SIPS
2008
IEEE
8 years 9 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
books