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JCP
2008
174views more  JCP 2008»
9 years 9 months ago
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
DAC
1997
ACM
10 years 1 months ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
James Kao, Anantha Chandrakasan, Dimitri Antoniadi...
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
10 years 2 months ago
On optimal physical synthesis of sleep transistors
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
Changbo Long, Jinjun Xiong, Lei He
DATE
2008
IEEE
132views Hardware» more  DATE 2008»
10 years 3 months ago
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
Ehsan Pakbaznia, Massoud Pedram
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
10 years 4 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
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