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ICDCN
2012
Springer
10 years 9 months ago
Lifting the Barriers - Reducing Latencies with Transparent Transactional Memory
Synchronization in distributed systems is expensive because, in general, threads must stall to obtain a lock or to operate on volatile data. Transactional memory, on the other hand...
Annette Bieniusa, Thomas Fuhrmann
TOCS
1998
83views more  TOCS 1998»
12 years 1 months ago
Using Value Prediction to Increase the Power of Speculative Execution Hardware
This paper presents an experimental and analytical study of value prediction and its impact on speculative execution in superscalar microprocessors. Value prediction is a new para...
Freddy Gabbay, Avi Mendelson
ISCA
2008
IEEE
185views Hardware» more  ISCA 2008»
12 years 1 months ago
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware
Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely...
Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chu...
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
12 years 5 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
12 years 5 months ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...
ICECCS
1995
IEEE
108views Hardware» more  ICECCS 1995»
12 years 5 months ago
Using speculative execution for fault tolerance in a real-time system
Achieving fault-tolerance using a primary-backup approach involves overhead of recovery such as activating the backup and propagating execution states, which may a ect the timelin...
Mohamed F. Younis, Grace Tsai, Thomas J. Marlowe, ...
CCGRID
2003
IEEE
12 years 5 months ago
Kernel Level Speculative DSM
Interprocess communication (IPC) is ubiquitous in today's computing world. One of the simplest mechanisms for IPC is shared memory. We present a system that enhances the Syst...
Cristian Tapus
ASPLOS
1992
ACM
12 years 6 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
KBSE
2003
IEEE
12 years 7 months ago
Unspeculation
Modern architectures, such as the Intel Itanium, support speculation, a hardware mechanism that allows the early execution of expensive operations—possibly even before it is kno...
Noah Snavely, Saumya K. Debray, Gregory R. Andrews
HPCA
2006
IEEE
12 years 8 months ago
Speculative synchronization and thread management for fine granularity threads
Performance of multithreaded programs is heavily influenced by the latencies of the thread management and synchronization operations. Improving these latencies becomes especially...
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gr...
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