Sciweavers

ICCAD
1994
IEEE
91views Hardware» more  ICCAD 1994»
13 years 8 months ago
A loosely coupled parallel algorithm for standard cell placement
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
Wern-Jieh Sun, Carl Sechen
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
13 years 10 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
13 years 10 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
13 years 10 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...