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ASYNC
2005
IEEE
132views Hardware» more  ASYNC 2005»
10 years 20 days ago
High Level Synthesis of Timed Asynchronous Circuits
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC speciļ¬cations to timed asynchronous gate-level circuits. The state-based logic synthes...
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...
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