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ICCAD
2007
IEEE
108views Hardware» more  ICCAD 2007»
14 years 1 months ago
A frequency-domain technique for statistical timing analysis of clock meshes
—We propose a frequency-domain modeling technique with applications on the statistical timing analysis of clock mesh/grid networks. Using transmission lines to model clock mesh e...
Ruilin Wang, Cheng-Kok Koh
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
14 years 1 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCD
2007
IEEE
120views Hardware» more  ICCD 2007»
14 years 1 months ago
Statistical timing analysis using Kernel smoothing
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...
VLSID
2005
IEEE
150views VLSI» more  VLSID 2005»
14 years 4 months ago
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
Baohua Wang, Pinaki Mazumder
DAC
2004
ACM
14 years 5 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
DAC
2004
ACM
14 years 5 months ago
Statistical timing analysis based on a timing yield model
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
Farid N. Najm, Noel Menezes
DAC
2003
ACM
14 years 5 months ago
Death, taxes and failing chips
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
Chandu Visweswariah
DAC
2002
ACM
14 years 5 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti...
DAC
2007
ACM
14 years 5 months ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that g...
Qunzeng Liu, Sachin S. Sapatnekar