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ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
13 years 9 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
13 years 9 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...