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ASPLOS
1992
ACM
13 years 8 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
13 years 8 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
EUROMICRO
1998
IEEE
13 years 8 months ago
Data Speculative Multithreaded Architecture
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Pedro Marcuello, Antonio González
IEEEPACT
1999
IEEE
13 years 8 months ago
MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors
This paper explores microarchitecture models for a simultaneous multithreaded processor with multimedia enhancements. We enhance a wide-issue superscalar processor by the simultan...
Heiko Oehring, Ulrich Sigmund, Theo Ungerer
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 9 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
DSN
2008
IEEE
13 years 11 months ago
Coverage of a microarchitecture-level fault check regimen in a superscalar processor
Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approac...
Vimal K. Reddy, Eric Rotenberg
ISPASS
2009
IEEE
13 years 11 months ago
Accurately approximating superscalar processor performance from traces
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
Kiyeon Lee, Shayne Evans, Sangyeun Cho