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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
10 years 9 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
MST
2002
107views more  MST 2002»
11 years 5 months ago
A Comparison of Asymptotically Scalable Superscalar Processors
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...
Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh
FAC
2000
124views more  FAC 2000»
11 years 5 months ago
Algebraic Models of Correctness for Microprocessors
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
Anthony C. J. Fox, Neal A. Harman
MICRO
1991
IEEE
126views Hardware» more  MICRO 1991»
11 years 8 months ago
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching
The performance of superscalar processors is more sensitive to the memory system delay than their single-issue predecessors. This paper examines alternative data access microarchi...
William Y. Chen, Scott A. Mahlke, Pohua P. Chang, ...
CF
2007
ACM
11 years 9 months ago
By-passing the out-of-order execution pipeline to increase energy-efficiency
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
Hans Vandierendonck, Philippe Manet, Thibault Dela...
MICRO
1992
IEEE
99views Hardware» more  MICRO 1992»
11 years 9 months ago
An investigation of the performance of various dynamic scheduling techniques
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...
Michael Butler, Yale N. Patt
INFOVIS
1999
IEEE
11 years 9 months ago
Visualizing Application Behavior on Superscalar Processors
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
Chris Stolte, Robert Bosch, Pat Hanrahan, Mendel R...
ICS
2001
Tsinghua U.
11 years 9 months ago
Reducing the complexity of the issue logic
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
Ramon Canal, Antonio González
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
11 years 10 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
11 years 11 months ago
Late-binding: enabling unordered load-store queues
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
Simha Sethumadhavan, Franziska Roesner, Joel S. Em...
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