ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
MST
2002
13 years 4 months ago
2002
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...
FAC
2000
13 years 4 months ago
2000
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
MICRO
1991
IEEE
13 years 7 months ago
1991
IEEE
The performance of superscalar processors is more sensitive to the memory system delay than their single-issue predecessors. This paper examines alternative data access microarchi...
CF
2007
ACM
13 years 8 months ago
2007
ACM
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
MICRO
1992
IEEE
13 years 8 months ago
1992
IEEE
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...
INFOVIS
1999
IEEE
13 years 8 months ago
1999
IEEE
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
ICS
2001
Tsinghua U.
13 years 8 months ago
2001
Tsinghua U.
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
ACMMSP
2004
ACM
13 years 9 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
ISCA
2007
IEEE
13 years 10 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...