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10 years 12 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
107views more  TVLSI 2002»
11 years 7 months ago
Low-power clock distribution using multiple voltages and reduced swings
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...
Jatuchai Pangjun, Sachin S. Sapatnekar
122views more  TVLSI 1998»
11 years 7 months ago
Algorithm-based low-power transform coding architectures: the multirate approach
—In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes...
An-Yeu Wu, K. J. Ray Liu
129views more  JCSC 2002»
11 years 8 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
119views more  TCAD 2008»
11 years 8 months ago
Bridging Fault Test Method With Adaptive Power Management Awareness
Abstract--A key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques ...
S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosin...
93views more  ENGL 2007»
11 years 8 months ago
A High Precision Bandgap Reference Used in Power Management ICs
—A 2.5V high precision BiCMOS bandgap reference with supply voltage range of 6V to 18V was proposed and realized. It could be applied to lots of Power Management ICs (Intergrated...
Gu Shurong, Wu Xiaobo, Yan Xiaolang
232views more  JCP 2008»
11 years 8 months ago
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira ...
170views Hardware» more  ISLPED 2010»
11 years 8 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...
202views Hardware» more  ISLPED 2010»
11 years 8 months ago
MODEST: a model for energy estimation under spatio-temporal variability
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
170views Hardware» more  ISQED 2010»
11 years 10 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...