Sciweavers

ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 5 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
EURODAC
1995
IEEE
182views VHDL» more  EURODAC 1995»
13 years 7 months ago
Delay modelling improvement for low voltage applications
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
Jean Michel Daga, Michel Robert, Daniel Auvergne
DELTA
2004
IEEE
13 years 7 months ago
Low Voltage CMOS op-amp with Rail-to-Rail Input/Output Swing
Abstract--As the supply voltage to a standard CMOS opamp is reduced, the input common mode range and the output swing get reduced drastically. Special biasing circuits have to be u...
S. V. Gopalaiah, A. P. Shivaprasad
ISLPED
1996
ACM
121views Hardware» more  ISLPED 1996»
13 years 7 months ago
A low power high performance switched-current multiplier
This paper presents an accurate switched-current multiplier, designed for 3.3V supply voltage, performing 0.625M multiplications per second with a maximum nonlinearity of 0.94%. Th...
Domine Leenaerts, G. H. M. Joordens, Johannes A. H...
ISLPED
1996
ACM
91views Hardware» more  ISLPED 1996»
13 years 7 months ago
Energy minimization using multiple supply voltages
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling pro...
Jui-Ming Chang, Massoud Pedram
DAC
1997
ACM
13 years 7 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
VTS
1998
IEEE
98views Hardware» more  VTS 1998»
13 years 7 months ago
Experimental Results for IDDQ and VLV Testing
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu,...
ICCAD
1998
IEEE
64views Hardware» more  ICCAD 1998»
13 years 8 months ago
Energy-efficiency in presence of deep submicron noise
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
Rajamohana Hegde, Naresh R. Shanbhag
ISSS
1999
IEEE
125views Hardware» more  ISSS 1999»
13 years 8 months ago
Real-Time Task Scheduling for a Variable Voltage Processor
This paper presents a real-time task scheduling technique with a variable voltage processor which can vary its supply voltage dynamically. Using such a processor, running tasks wi...
Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
DATE
2002
IEEE
156views Hardware» more  DATE 2002»
13 years 8 months ago
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
Chris H. Kim, Kaushik Roy