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    ISCA
    2006
    IEEE
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    Area-Performance Trade-offs in Tiled Dataflow Architectures
    13 years 4 months ago
    Area-Performance Trade-offs in Tiled Dataflow Architectures
    Download  wavescalar.cs.washington.edu
    : Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
    Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
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