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CC
2012
Springer
1 months 8 days ago
Programming Paradigm Driven Heap Analysis
The computational cost and precision of a shape style heap analysis is highly dependent on the way method calls are handled. This paper introduces a new approach to analyzing metho...
Mark Marron, Ondrej Lhoták, Anindya Banerje...
CC
2012
Springer
1 months 8 days ago
Parallel Replication-Based Points-To Analysis
Pointer analysis is one of the most important static analyses during compilation. While several enhancements have been made to scale pointer analysis, the work on parallelizing the...
Sandeep Putta, Rupesh Nasre
CC
2012
Springer
1 months 8 days ago
Sambamba: A Runtime System for Online Adaptive Parallelization
Abstract. How can we exploit a microprocessor as efficiently as possible? The “classic” approach is static optimization at compile-time, optimizing a program for all possible u...
Kevin Streit, Clemens Hammacher, Andreas Zeller, S...
CC
2012
Springer
1 months 8 days ago
Improving Performance of OpenCL on CPUs
Abstract. Data-parallel languages like OpenCL and CUDA are an important means to exploit the computational power of today’s computing devices. In this paper, we deal with two asp...
Ralf Karrenberg, Sebastian Hack
HIPEAC
2011
Springer
5 months 6 days ago
A workload-aware mapping approach for data-parallel programs
Much compiler-orientated work in the area of mapping parallel programs to parallel architectures has ignored the issue of external workload. Given that the majority of platforms w...
Dominik Grewe, Zheng Wang, Michael F. P. O'Boyle
HIPEAC
2011
Springer
5 months 6 days ago
TypeCastor: demystify dynamic typing of JavaScript applications
Dynamic typing is a barrier for JavaScript applications to achieve high performance. Compared with statically typed languages, the major overhead of dynamic typing comes from runt...
Shisheng Li, Buqi Cheng, Xiao-Feng Li
HIPEAC
2011
Springer
5 months 6 days ago
Decoupled zero-compressed memory
For each computer system generation, there are always applications or workloads for which the main memory size is the major limitation. On the other hand, in many cases, one could...
Julien Dusser, André Seznec
HIPEAC
2011
Springer
5 months 6 days ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
CASES
2011
ACM
5 months 16 days ago
Cost-effective safety and fault localization using distributed temporal redundancy
Cost pressure is driving vendors of safety-critical systems to integrate previously distributed systems. One natural approach we have previous introduced is On-Demand Redundancy (...
Brett H. Meyer, Benton H. Calhoun, John Lach, Kevi...
CASES
2011
ACM
5 months 16 days ago
Enabling parametric feasibility analysis in real-time calculus driven performance evaluation
This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarc...
Alena Simalatsar, Yusi Ramadian, Kai Lampka, Simon...
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