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TCAD
2002
128views more  TCAD 2002»
10 years 2 months ago
Preferred direction Steiner trees
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
Mehmet Can Yildiz, Patrick H. Madden
TCAD
2002
92views more  TCAD 2002»
10 years 2 months ago
Design of reconfigurable composite microsystems based on hardware/software codesign principles
Abstract--Composite microsystems that integrate mechanical and fluidic components with electronics are emerging as the next generation of system-on-a-chip. Custom microsystems are ...
Tianhao Zhang, Krishnendu Chakrabarty, Richard B. ...
TCAD
2002
134views more  TCAD 2002»
10 years 2 months ago
DS-LFSR: a BIST TPG for low switching activity
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
Seongmoon Wang, Sandeep K. Gupta
TCAD
2002
123views more  TCAD 2002»
10 years 2 months ago
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
Abstract--Recent study shows that the nonuniform thermal distribution not only has an impact on the substrate but also interconnects. Hence, three
Ting-Yuan Wang, Charlie Chung-Ping Chen
TCAD
2002
77views more  TCAD 2002»
10 years 2 months ago
Fast and exact transistor sizing based on iterative relaxation
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
TCAD
2002
106views more  TCAD 2002»
10 years 2 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...
TCAD
2002
104views more  TCAD 2002»
10 years 2 months ago
A framework for testing special-purpose memories
Piotr R. Sidorowicz, Janusz A. Brzozowski
TCAD
2002
93views more  TCAD 2002»
10 years 2 months ago
Hierarchical buffered routing tree generation
Abstract--This paper presents a solution to the problem of performance-driven buffered routing tree generation for VLSI circuits. Using a novel bottom-up construction algorithm and...
Amir H. Salek, Jinan Lou, Massoud Pedram
TCAD
2002
104views more  TCAD 2002»
10 years 2 months ago
An instruction-level energy model for embedded VLIW architectures
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
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