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TCAD
2010
136views more  TCAD 2010»
11 years 4 months ago
Bounded Model Debugging
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
Brian Keng, Sean Safarpour, Andreas G. Veneris
TCAD
2010
154views more  TCAD 2010»
11 years 4 months ago
Automated Design Debugging With Maximum Satisfiability
As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug soluti...
Yibin Chen, Sean Safarpour, João Marques-Si...
TCAD
2010
154views more  TCAD 2010»
11 years 4 months ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
TCAD
2010
116views more  TCAD 2010»
11 years 4 months ago
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
Anand Rajaram, David Z. Pan
TCAD
2010
107views more  TCAD 2010»
11 years 4 months ago
Evaluating Statistical Power Optimization
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this ...
Jason Cong, Puneet Gupta, John Lee
TCAD
2010
160views more  TCAD 2010»
11 years 4 months ago
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
TCAD
2010
164views more  TCAD 2010»
11 years 4 months ago
Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. How...
Javid Jaffari, Mohab Anis
TCAD
2010
124views more  TCAD 2010»
11 years 4 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
TCAD
2010
194views more  TCAD 2010»
11 years 4 months ago
Layout Decomposition Approaches for Double Patterning Lithography
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...
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